1. Field of the Invention
The present invention relates to a driver circuit and method for differential signaling, more particularly, to differential signaling using reduced amplitude signals.
2. Description of the Related Art
In order to satisfy the requirement of size reduction, recent portable appliances with a LCD (liquid crystal display) panel, such as cell phones and digital cameras, often adopt LVDS (Low Voltage Differential Signaling), which allows transmitting digital signals to a LCD driver with a reduced number of signal lines while reducing EMI (Electromagnetic Interference). The LVDS is a reduced amplitude interface standardized as the TIA/EIA644 standard by TIA/EIA (Telecommunication Industry Association/Electric Industries Alliance).
The LVDS transmission medium, such as a cable and a PCB (printed circuit board) trace, requires termination with an appropriate impedance to form a complete current loop. This requirement does not depend on whether the LVDS transmission medium is a cable or a PCB trace. Inappropriate termination may cause signal interference due to the signal reflection at the end of the cable or the PCB trace; suitable termination is required for reducing undesired electromagnetic wave emission and improving signal quality. In order to avoid signal reflection, the LVDS transmission medium requires a terminating resistor which matches the differential impedance of the cable or the PCB trace. In general, a 100Ω resistor is used as a terminating resistor of an LVDS transmission medium. The terminating resistor is desirably connected between the two signal lines at a position as close as possible to the inputs of the LVDS receiver.
It is important to feed differential signals with stable voltage levels to an LVDS transmission medium. The differential signal amplitude and the output offset voltage (or common mode voltage), which is the average of the voltage levels of the differential signals, are required to be in predetermined ranges. Specifically, the IEEE standard 1596.3-1996 defines allowed variations in the differential signals; for an output offset voltage Vcm of 1.2V, the allowed variation in the differential signals is ±0.075V. There is a need for a technique to provide an LVDS driver that reduces variations in the differential signal amplitude and the output offset voltage.
International Publication WO 03/049291 A1 (hereinafter, the '291 international publication) and the corresponding U.S. Pat. No. 7,129,756 disclose a LVDS line driver for generating differential signals with reduced variations. FIG. 4 is a circuit diagram of the disclosed line driver. The line driver shown in FIG. 4 is provided with a driver circuit 10 and a replica circuit 20 for controlling the operation of the driver circuit 10.
The driver circuit 10 includes an output circuit composed of NMOS transistors N11 to N14, and NMOS transistors N15 and N16. The NMOS transistors N11 to N14 each receive a differential signal Vin1 or Vin2 on the gate thereof, and provide switching in response to the received differential signal Vin1 or Vin2. The NMOS transistor N16 is connected between a power line of the power supply level VDD and the drains of the NMOS transistors N11 and N13. The NMOS transistor N15 is connected between a power line of the ground level GND and the sources of the NMOS transistors N12 and N14. A reference voltage Vref2 is supplied to the gate of the NMOS transistor N15 from the output terminal 204 of the replica circuit 20 to control the operating current through the NMOS transistor N15. The gate of the NMOS transistor N16 is connected with the output terminal 203 of the replica circuit 20, and the operation current through the NMOS transistor N15 is controlled depending on the voltage received from the output terminal 203.
The replica circuit 20 is provided with NMOS transistors N17 to N20, and a pair of resistors nRT/2. The size of the NMOS transistors N17 to N20 is 1/n times as large as that of the NMOS transistors N11 to N16. The resistance of the resistors nRT/2 is (n/2) times as large as that of the terminating resistor RT provided for the receiver. The NMOS transistor N20 of the replica circuit 20 and the NMOS transistor N15 of the driver circuit 10 operate as a current mirror circuit, and the amplitude of the current through the transistor N20 is 1/n times as large as that of the current through the NMOS transistor N15.
The resistors nRT/2 are serially connected with each other on the connection node 205, and function as a replica of the terminating resistor RT. The NMOS transistors N18 and N19, corresponding to the NMOS transistors N11 to N14, are connected with the serially-connected resistors nRT/2. It should be noted that the gates of the NMOS transistors N18 and N19 are kept pulled up to the power supply level VDD, and therefore the NMOS transistors N18 and N19 are continuously turned on. The gate of the NMOS transistor N17 is connected with the output terminal of an operation amplifier OP10, and the drain of the NMOS transistor N17 is pulled up to the power supply level VDD. A reference voltage Vref1 is fed to the non-inverting input of the operation amplifier OP10, and the inverting input is connected with the connection node 205 of the resistors nRT/2. The operation amplifier OP10 provides feedback control of the voltage level of the output terminal 203 so as to regulate the voltage level of the connection node 205 to the reference voltage Vref1. The operation current through the NMOS transistor N16 is determined by the voltage level of the output terminal 203. Additionally, the drain currents of the NMOS transistors N15 and N20 are controlled by the reference voltage Vref2. In other words, the operation currents of the driver circuit 10 and the replica circuit 20 are controlled depending on the reference voltage Vref2.
The above-described configuration allows controlling the gate voltage of the NMOS transistor N16, which operates as a current source within the driver current 10, so as to reduce the difference between the voltage level of the connection node 205 and the reference voltage Vref1, thereby controlling the voltage applied across the terminating resistor RT.
However, the inventor has recognized that the line driver disclosed in the '291 international publication suffers from large variations in the amplitudes of the differential output signals and the output offset voltage, due to the manufacture variations of the replica circuit 20 and the interface between the driver circuit 10 and the replica circuit 20.
Japanese Laid-Open Patent Applications Nos. JP-A 2005-303830 (hereinafter, the '830 application) and JP-A 2006-60320 (hereinafter, the '320 application) disclose another driver configuration in which two operation amplifiers receiving different reference voltages respectively control two current sources within a driver circuit to thereby reduce the variations in the differential output signals. More specifically, one of the operation amplifiers receives an intermediate voltage which is generated as the average of the voltage levels of the differential output signals and controls one of the two current sources in response to the comparison of the intermediate voltage with the reference voltage. The other of the operation amplifiers is connected with a selector circuit that provides a connection with a selected one of the two output terminals of the driver circuit in response to the voltage level of the input signal fed to the driver circuit. The other operation amplifier controls the other of the current source in response to the comparison of the voltage received from the selected output terminal and the reference voltage. Controlling the two current sources within the driver circuit effectively reduces the variations in the differential output signals.
However, the inventor has recognized that the driver circuits disclosed in the '830 and '320 applications suffers from a problem that it takes long time to stabilize the voltage levels of the differential output signals within a desired range. In the worst case, the differential output signals may settle at voltage levels out of the desired range. The driver circuits disclosed in the '830 and '320 applications uses a selector circuit to select the voltage fed to the operation amplifier that control the current source within the driver circuit. Therefore, the voltage received by the operation amplifier may largely change. This undesirably increases the duration of time necessary for stabilization of the voltage levels of the differential output signals.